1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming diffusion breaks on integrated circuit (IC) products comprised of FinFET devices and the resulting IC products.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a traditional FinFET device. In this example, the FinFET device 10 includes three illustrative fins 14, a gate structure 16, sidewall spacers 18 and a gate cap 20. The gate structure 16 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device 10. The fins 14 have a three-dimensional configuration: a height 14H, a width 14W and an axial length 14L. The axial length 14L of the fins 14 corresponds to the direction of current travel, i.e., the gate length (GL) of the device 10 when it is operational. The gate width (GW) of the overall device is also depicted in FIG. 1A. The portions of the fins 14 covered by the gate structure 16 is the channel region of the FinFET device 10. In a conventional process flow, the portions of the fins 14 that are positioned outside of the spacers 18, i.e., in the source/drain regions of the device 10, may be increased in size or even merged together (a situation not shown in FIG. 1A) by performing one or more epitaxial growth processes to grow additional semiconductor material on the fins in the source/drain regions of the device 10.
FIG. 1B is a cross-sectional view of the device 10 taken through the gate structure 16 in the gate width (GW) direction of the device with additional layers of material and structures not depicted in FIG. 1A. As shown therein, the device 10 includes a recessed layer of insulating material 22 positioned between the fins 14, another layer of insulating material 24 that is positioned above the gate cap layer 20 and a gate contact structure 28 that is conductively coupled to the gate structure 16. The device 10 depicted in FIG. 1B is a tri-gate (or triple gate) FinFET device. That is, during operation, a very shallow conductive region 26 (shown only on the middle fin in FIG. 1B) will be established that provides a path or channel for current to flow from the source region to the drain region. The conductive region 26 forms inward of the side surfaces 14S and below the top surface 14T of the fins 14.
For many early device technology generations, the gate electrode structures of most transistor elements was comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate electrode stacks comprising alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 14-32 nm, gate structures comprised of a high-k gate insulation layer (k value of 10 or greater) and one or more metal layers, a so-called high-k dielectric/metal gate (HK/MG) configuration, have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. In the replacement gate technique, a so-called “dummy” or sacrificial gate structure is initially formed and remains in place as many process operations are performed to form the device, e.g., the formation of doped source/drain regions, formation of epi semiconductor material in the source/drain regions of the device, performing an anneal process to repair damage to the substrate caused by the ion implantation processes and to activate the implanted dopant materials, etc. At some point in the process flow, the sacrificial gate structure is removed to define a gate cavity where the final HK/MG replacement gate structure for the device is formed.
The various transistor devices that are formed for an IC product must be electrically isolated from one another to properly function in an electrical circuit. Typically, this is accomplished by forming a trench in the substrate 12, and filling the trench with an insulating material, such as silicon dioxide. However, the formation of such trenches consumes very valuable plot space on the substrate 12. Moreover, in some applications, such as those integrated circuit products employing FinFET transistor devices, as device sizes have decreased, and packing densities have increased, it is sometimes difficult to form the desired isolation region made of an insulating material.
FIG. 1C is a simplistic plan view of an integrated circuit product that has two logic cells positioned side by side on a substrate, wherein the circuits are manufactured using FinFET devices. FIG. 1C depicts the fins, the active gates and the dummy gates of the logic cells. Typically, the fins are formed uniformly across the entire substrate (i.e., a “sea of fins”). Thereafter, portions of the fins are removed to define regions where isolation regions will be formed to electrically isolate the various devices. Cutting the desired portions of the fins is typically accomplished by forming a so-called “fin cut” patterned etch mask with openings corresponding to the portions of the fins to be removed. The space previously occupied by the removed portions of the fins is then filled with an insulating material. After the fins are cut, and the isolation regions are formed, the gate structures are then formed across the fins. In the case where a replacement gate process is used, the initial gate structures are sacrificial gate structures that will subsequently be removed and replaced with final gate structures for the devices. As mentioned above, several process operations are performed after the formation of the sacrificial gate structures, e.g., the formation of epi semiconductor material in the source/drain regions of the device. When the epi semiconductor material is formed in the source/drain regions, it is important that the epi material not form in unwanted areas of the devices so as to not create a multitude of problems, e.g., growing around the end of a gate structure so as to create a short circuit between the source region and drain region, bridging the space between two adjacent active regions, etc. Thus, with reference to FIG. 1C, when the fins are cut, the cut is located such that the cut ends of the fins will be positioned under the dummy gate structures when they are formed. This is sometimes referred to as the fins being “tucked” in the sense that the cut end of the fin is positioned under or “tucked under” the dummy gate structure. Such a tucked fin arrangement is required on integrated circuits having arrangements similar to that depicted in FIG. 1C so as to prevent the undesirable formation of epi semiconductor material in the space between the two dummy gates. Unfortunately, producing such a tucked fin arrangement requires the use of two dummy gate lines. Having two dummy gate lines at each cell boundary of an integrated circuit product consumes valuable plot space and reduces cell efficiency.
The present disclosure is directed to methods of forming diffusion breaks on IC products comprised of FinFET devices and the resulting products that may solve or reduce one or more of the problems identified above.